When the CPU is reset it starts up in emulation mode and expects to find the RESET vector at logical address $FFFC (which physical offset within the ROM that corresponds to depends on the memory mapping mode). Native mode: $FFE4: COP (co-processor interrupt) There's also the native mode, where you've got 16-bit registers and all that jazz. For backwards compatibility, the 65C816 includes an emulation mode that is binary compatible with the 6502 (actually the 65C02). The SNES's CPU is based on the 65C816, which is sort of an evolution of the 6502.
If this is the case, does that mean that the first byte of the file (after the header) is an opcode? The CPU has no way of knowing that and proceeds regardless, executing memory content which was never meant to executed and performing essentially random operations.Īn excellent resource for understanding how this is all put together is The Elements of Computing Systems which is a book but most of the content are available from that web site. Execution may change the PC in the case of a jump for example but at the end of execution, the PC will be pointing at the op-code byte of the next instruction to execute and the cycle, called the fetch-execute cycle, continues.īugs in programs are quite often due to the fact that the PC is changed to a value which is not the the start of an instruction written by the programmer/compiler. The CPU then performs the operations determined by the op-code byte and its operands, this is called instruction execution.
Once a complete instruction is fetched the PC will be pointing at the op-code for the next instruction. The op-code is examined and any necessary operand bytes are fetched, always from memory pointed to by PC which is incremented for each one. The processor fetches the op-code byte from the address in the PC and increments the PC. The first byte of every instruction is the op-code byte its coding determines what the instruction will do and how many operand bytes are required. On reset, the PC is set to a fixed value where execution begins. The processor has a PC (Program Counter) register containing the address of the next instruction to be executed.
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